Semiconductor devices

ABSTRACT

A semiconductor device includes a control circuit and an address generation circuit. The control circuit generates a write column address signal, a write bank selection signal and an internal write bank selection signal from a command/address signal during a write operation. The control circuit also generates a read column address signal, a read bank selection signal and an internal read bank selection signal from the command/address signal during a read operation. The address generation circuit outputs the write column address signal as a bank group address signal in synchronization with the write bank selection signal and the internal write bank selection signal or outputs the read column address signal as the bank group address signal in synchronization with the read bank selection signal and the internal read bank selection signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C 119(a) to KoreanApplication No. 10-2018-0130179, filed on Oct. 29, 2018, which isincorporated herein by reference in its entirety.

BACKGROUND 1. Technical Field

Embodiments of the present disclosure generally relate to semiconductordevices relating to a column operation.

2. Related Art

In general, each of semiconductor devices such as dynamic random accessmemory (DRAM) devices may include a plurality of bank groups comprisedof cell arrays which are selected by addresses. Each of the bank groupsmay be realized to include a plurality of banks. The semiconductordevice may select any one of the plurality of bank groups and mayperform a column operation for outputting data stored in a cell arrayincluded in the selected bank group through input/output (I/O) lines.

SUMMARY

According to an embodiment, a semiconductor device includes a controlcircuit and an address generation circuit. The control circuit generatesa write column address signal from a command/address signal during awrite operation and generates a write bank selection signal and aninternal write bank selection signal from the command/address signalduring the write operation. The control circuit also generates a readcolumn address signal from the command/address signal during a readoperation and generates a read bank selection signal and an internalread bank selection signal from the command/address signal during theread operation. The write bank selection signal and the internal writebank selection signal are sequentially enabled, and wherein the readbank selection signal and the internal read bank selection signal aresequentially enabled. The address generation circuit outputs the writecolumn address signal as a bank group address signal in synchronizationwith the write bank selection signal and the internal write bankselection signal or outputs the read column address signal as the bankgroup address signal in synchronization with the read bank selectionsignal and the internal read bank selection signal.

According to an embodiment, a semiconductor device includes a controlcircuit, an address generation circuit and a core circuit. The controlcircuit generates first and second write column address signals, firstand second write bank selection signals and first and second internalwrite bank selection signals from a command/address signal during awrite operation. The control circuit also generates first and secondread column address signals, first and second read bank selectionsignals and first and second internal read bank selection signals fromthe command/address signal during a read operation. The addressgeneration circuit outputs the first and second write column addresssignals as first and second bank group address signals insynchronization with the first and second write bank selection signalsand the first and second internal write bank selection signals oroutputs the first and second read column address signals as the firstand second bank group address signals in synchronization with the firstand second read bank selection signals and the first and second internalread bank selection signals. The core circuit includes a first bankgroup and a second bank group. The first bank group performs the writeoperation and the read operation when the first bank group addresssignal is enabled, and the second bank group performs the writeoperation and the read operation when the second bank group addresssignal is enabled.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of asemiconductor device according to an embodiment of the presentdisclosure.

FIG. 2 is a block diagram illustrating a configuration of a writecontrol circuit included in the semiconductor device of FIG. 1.

FIG. 3 is a block diagram illustrating a configuration of a write bankselection signal generation circuit included in the write controlcircuit of FIG. 2.

FIG. 4 is a circuit diagram illustrating a configuration of a firstwrite bank selection signal generation circuit included in the writebank selection signal generation circuit of FIG. 3.

FIG. 5 is a circuit diagram illustrating a configuration of a secondwrite bank selection signal generation circuit included in the writebank selection signal generation circuit of FIG. 3.

FIG. 6 is a circuit diagram illustrating a configuration of a thirdwrite bank selection signal generation circuit included in the writebank selection signal generation circuit of FIG. 3.

FIG. 7 is a circuit diagram illustrating a configuration of a fourthwrite bank selection signal generation circuit included in the writebank selection signal generation circuit of FIG. 3.

FIG. 8 is a block diagram illustrating a configuration of a read controlcircuit included in the semiconductor device of FIG. 1.

FIG. 9 is a block diagram illustrating a configuration of a read bankselection signal generation circuit included in the read control circuitof FIG. 8.

FIG. 10 is a circuit diagram illustrating a configuration of a firstread bank selection signal generation circuit included in the read bankselection signal generation circuit of FIG. 9.

FIG. 11 is a circuit diagram illustrating a configuration of a secondread bank selection signal generation circuit included in the read bankselection signal generation circuit of FIG. 9.

FIG. 12 is a circuit diagram illustrating a configuration of a thirdread bank selection signal generation circuit included in the read bankselection signal generation circuit of FIG. 9.

FIG. 13 is a circuit diagram illustrating a configuration of a fourthread bank selection signal generation circuit included in the read bankselection signal generation circuit of FIG. 9.

FIG. 14 is a block diagram illustrating a configuration of an addressgeneration circuit included in the semiconductor device of FIG. 1.

FIG. 15 is a block diagram illustrating a configuration of a firstaddress generation circuit included in the address generation circuit ofFIG. 14.

FIG. 16 is a circuit diagram illustrating a configuration of a firstaddress output circuit included in the first address generation circuitof FIG. 15.

FIG. 17 is a block diagram illustrating a configuration of a secondaddress generation circuit included in the address generation circuit ofFIG. 14.

FIG. 18 is a circuit diagram illustrating a configuration of a fifthaddress output circuit included in the second address generation circuitof FIG. 17.

FIG. 19 is a timing diagram illustrating an operation of a semiconductordevice according to an embodiment of the present disclosure.

FIG. 20 is a block diagram illustrating a configuration of an electronicsystem including the semiconductor device illustrated in FIGS. 1 to 19.

DETAILED DESCRIPTION

Various embodiments of the present disclosure will be describedhereinafter with reference to the accompanying drawings. However, theembodiments described herein are for illustrative purposes only and arenot intended to limit the scope of the present disclosure.

In the present disclosure, semiconductor devices may provide a bankgroup mode, an 8-bank mode and a 16-bank mode. A bank group may includea plurality of banks. For example, the bank group may include fourbanks. In the bank group mode, a column operation for one bank includedin the bank group may be performed by one command. In the 8-bank mode,column operations for two banks respectively included in separate bankgroups are sequentially performed by one command. In the 16-bank mode,column operations for four banks respectively included in separate bankgroups are sequentially performed by one command.

As illustrated in FIG. 1, a semiconductor device according to anembodiment may include a command pulse generation circuit 1, a flagsignal generation circuit 2, a column control pulse generation circuit3, a control circuit 4, an address generation circuit 5 and a corecircuit 6.

The command pulse generation circuit 1 may generate a first writecommand pulse EWT1, a second write command pulse EWT2, a first readcommand pulse ERD1 and a second read command pulse ERD2 according tofirst to N^(th) command/address signals CA<1:N>, an internal clocksignal ICLK and an inverted internal clock signal ICLKB. The first toN^(th) command/address signals CA<1:N> may include a command and anaddress provided by an external device. The internal clock signal ICLKmay be toggled in synchronization with a rising edge of a clock signal(not shown) provided by an external device. The inverted internal clocksignal ICLKB may be toggled in synchronization with a falling edge of aclock signal (not shown) provided by an external device. The number ‘N’of bits included in the first to N^(th) command/address signals CA<1:N>may be set to be different according to the embodiments.

The command pulse generation circuit 1 may decode the first to N^(th)command/address signals CA<1:N> in synchronization with the internalclock signal ICLK or the inverted internal clock signal ICLKB togenerate the first write command pulse EWT1 and the second write commandpulse EWT2 for performing a write operation. According to an embodiment,in order to perform the write operation, the command pulse generationcircuit 1 may decode the first to N^(th) command/address signals CA<1:N>in synchronization with the internal clock signal ICLK to generate thefirst write command pulse EWT1 and may then shift the first writecommand pulse EWT1 in synchronization with the inverted internal clocksignal ICLKB to generate the second write command pulse EWT2. A point oftime when the first write command pulse EWT1 is generated to perform thewrite operation may be determined as a point of time when the first toN^(th) command/address signals CA<1:N> having a logic level combinationfor performing the write operation are inputted to the command pulsegeneration circuit 1 in synchronization with a rising edge of theinternal clock signal ICLK.

The command pulse generation circuit 1 may decode the first to N^(th)command/address signals CA<1:N> in synchronization with the internalclock signal ICLK or the inverted internal clock signal ICLKB togenerate the first read command pulse ERD1 and the second read commandpulse ERD2 for performing a read operation. According to an embodiment,in order to perform the read operation, the command pulse generationcircuit 1 may decode the first to N^(th) command/address signals CA<1:N>in synchronization with the internal clock signal ICLK to generate thefirst read command pulse ERD1 and may then shift the first read commandpulse ERD1 in synchronization with the inverted internal clock signalICLKB to generate the second read command pulse ERD2. A point of timewhen the first read command pulse ERD1 is generated to perform the readoperation may be determined as a point of time when the first to N^(th)command/address signals CA<1:N> having a logic level combination forperforming the read operation are inputted to the command pulsegeneration circuit 1 in synchronization with a rising edge of theinternal clock signal ICLK.

The flag signal generation circuit 2 may generate a write flag signalWTF, an internal write flag signal IWTF, a read flag signal RDF and aninternal read flag signal IRDF according to the first write commandpulse EWT1 and the first read command pulse ERD1.

The flag signal generation circuit 2 may generate the write flag signalWTF after a predetermined period elapses from a point of time when thefirst write command pulse EWT1 is created. The flag signal generationcircuit 2 may shift the first write command pulse EWT1 by thepredetermined period to generate the write flag signal WTF. Thepredetermined period for shifting the first write command pulse EWT1 maybe set to be different according to the embodiments. The flag signalgeneration circuit 2 may shift the write flag signal WTF by apredetermined period to generate the internal write flag signal IWTF.The predetermined period for shifting the write flag signal WTF may be aperiod which is set to perform a column operation according to a writelatency. The predetermined period for shifting the write flag signal WTFmay be set to be different according to the embodiments.

The word “predetermined” as used herein with respect to a parameter,such as a predetermined period, means that a value for the parameter isdetermined prior to the parameter being used in a process or algorithm.For some embodiments, the value for the parameter is determined beforethe process or algorithm begins. In other embodiments, the value for theparameter is determined during the process or algorithm but before theparameter is used in the process or algorithm.

The flag signal generation circuit 2 may generate the read flag signalRDF after a predetermined period elapses from a point of time when thefirst read command pulse ERD1 is created. The flag signal generationcircuit 2 may shift the first read command pulse ERD1 by thepredetermined period to generate the read flag signal RDF. Thepredetermined period for shifting the first read command pulse ERD1 maybe set according to a read latency. The predetermined period forshifting the first read command pulse ERD1 may be set to be differentaccording to the embodiments. The flag signal generation circuit 2 mayshift the read flag signal RDF by a predetermined period to generate theinternal read flag signal IRDF. The predetermined period for shiftingthe read flag signal RDF may be a period which is set to perform thecolumn operation according to a burst length. The predetermined periodfor shifting the read flag signal RDF may be set to be differentaccording to the embodiments. In some other embodiments, the flag signalgeneration circuit 2 may be realized to generate the write flag signalWTF, the internal write flag signal IWTF, the read flag signal RDF andthe internal read flag signal IRDF according to the second write commandpulse EWT2 and the second read command pulse ERD2.

The column control pulse generation circuit 3 may generate a writecolumn control pulse WTAYP, an internal write column control pulseIWTAYP, a read column control pulse RDAYP and an internal read columncontrol pulse IRDAYP according to the second write command pulse EWT2and the second read command pulse ERD2.

The column control pulse generation circuit 3 may generate the writecolumn control pulse WTAYP and the internal write column control pulseIWTAYP if the second write command pulse EWT2 is enabled. The columncontrol pulse generation circuit 3 may sequentially generate the writecolumn control pulse WTAYP and the internal write column control pulseIWTAYP after a predetermined period elapses from a point of time whenthe second write command pulse EWT2 is created. The column control pulsegeneration circuit 3 may shift the second write command pulse EWT2 bythe predetermined period to generate the write column control pulseWTAYP. The predetermined period for shifting the second write commandpulse EWT2 may be set according to the write latency. The predeterminedperiod for shifting the second write command pulse EWT2 may be set to bedifferent according to the embodiments. The column control pulsegeneration circuit 3 may shift the write column control pulse WTAYP by apredetermine period to generate the internal write column control pulseIWTAYP. The predetermine period for shifting the write column controlpulse WTAYP may be a period which is set to perform the column operationaccording to the burst length. The predetermine period for shifting thewrite column control pulse WTAYP may be set to be different according tothe embodiments.

The column control pulse generation circuit 3 may generate the readcolumn control pulse RDAYP and the internal read column control pulseIRDAYP in response to the second read command pulse ERD2. The columncontrol pulse generation circuit 3 may sequentially generate the readcolumn control pulse RDAYP and the internal read column control pulseIRDAYP after a predetermined period elapses from a point of time whenthe second read command pulse ERD2 is created. The column control pulsegeneration circuit 3 may shift the second read command pulse ERD2 by thepredetermined period to generate the read column control pulse RDAYP.The predetermined period for shifting the second read command pulse ERD2may be set according to the read latency. The predetermined period forshifting the second read command pulse ERD2 may be set to be differentaccording to the embodiments. The column control pulse generationcircuit 3 may shift the read column control pulse RDAYP by apredetermined period to generate the internal read column control pulseIRDAYP. The predetermined period for shifting the read column controlpulse RDAYP may be a period which is set to perform the column operationaccording to the burst length. The predetermined period for shifting theread column control pulse RDAYP may be set to be different according tothe embodiments. In some other embodiments, the column control pulsegeneration circuit 3 may be realized to generate the write columncontrol pulse WTAYP, the internal write column control pulse IWTAYP, theread column control pulse RDAYP and the internal read column controlpulse IRDAYP according to the first write command pulse EWT1 and thefirst read command pulse ERD1.

The control circuit 4 may include a write control circuit 10 and a readcontrol circuit 20.

The write control circuit 10 may be synchronized with the write columncontrol pulse WTAYP and the internal write column control pulse IWTAYPto generate first to fourth write column address signals WC<1:4> fromthe first to N^(th) command/address signals CA<1:N>.

The write control circuit 10 may be synchronized with the write columncontrol pulse WTAYP and the internal write column control pulse IWTAYPto generate first to fourth write bank selection signals ALW<1:4> andfirst to fourth internal write bank selection signals IALW<1:4> from thefirst to N^(th) command/address signals CA<1:N>. The write controlcircuit 10 may be synchronized with the write flag signal WTF and theinternal write flag signal IWTF to latch the first to N^(th)command/address signals CA<1:N>. The write control circuit 10 may besynchronized with the write column control pulse WTAYP and the internalwrite column control pulse IWTAYP to generate the first to fourth writebank selection signals ALW<1:4> and the first to fourth internal writebank selection signals IALW<1:4> from the latched signals of the firstto N^(th)command/address signals CA<1:N>.

The read control circuit 20 may be synchronized with the read columncontrol pulse RDAYP and the internal read column control pulse IRDAYP togenerate first to fourth read column address signals RC<1:4> from thefirst to N^(th) command/address signals CA<1:N>.

The read control circuit 20 may be synchronized with the read columncontrol pulse RDAYP and the internal read column control pulse IRDAYP togenerate first to fourth read bank selection signals ALR<1:4> and firstto fourth internal read bank selection signals IALR<1:4> from the firstto N^(th) command/address signals CA<1:N>. The read control circuit 20may be synchronized with the read flag signal RDF and the internal readflag signal IRDF to latch the first to N^(th) command/address signalsCA<1:N>. The read control circuit 20 may be synchronized with the readcolumn control pulse RDAYP and the internal read column control pulseIRDAYP to generate the first to fourth read bank selection signalsALR<1:4> and the first to fourth internal read bank selection signalsIALR<1:4> from the latched signals of the first to N^(th)command/address signals CA<1:N>.

The control circuit 4 having an aforementioned configuration maygenerate the first to fourth write column address signals WC<1:4> fromthe first to N^(th) command/address signals CA<1:N> to perform the writeoperation. The control circuit 4 may generate the first to fourth writebank selection signals ALW<1:4> and the first to fourth internal writebank selection signals IALW<1:4> from the first to N^(th)command/address signals CA<1:N> to perform the write operation. Thecontrol circuit 4 may generate the first to fourth read column addresssignals RC<1:4> from the first to N^(th) command/address signals CA<1:N>to perform the read operation. The control circuit 4 may generate thefirst to fourth read bank selection signals ALR<1:4> and the first tofourth internal read bank selection signals IALR<1:4> from the first toN^(th) command/address signals CA<1:N> to perform the read operation.

The address generation circuit 5 may be synchronized with the first tofourth write bank selection signals ALW<1:4> and the first to fourthinternal write bank selection signals IALW<1:4> to output the first tofourth write column address signals WC<1:4> as first bank group addresssignals C1_BG<1>, C2_BG<1>, C3_BG<1> and C4_BG<1>. The addressgeneration circuit 5 may be synchronized with the first to fourth writebank selection signals ALW<1:4> and the first to fourth internal writebank selection signals IALW<1:4> to output the first to fourth writecolumn address signals WC<1:4> as second bank group address signalsC1_BG<2>, C2_BG<2>, C3_BG<2> and C4_BG<2>. The address generationcircuit 5 may be synchronized with the first to fourth write bankselection signals ALW<1:4> and the first to fourth internal write bankselection signals IALW<1:4> to output the first to fourth write columnaddress signals WC<1:4> as third bank group address signals C1_BG<3>,C2_BG<3>, C3_BG<3> and C4_BG<3>. The address generation circuit 5 may besynchronized with the first to fourth write bank selection signalsALW<1:4> and the first to fourth internal write bank selection signalsIALW<1:4> to output the first to fourth write column address signalsWC<1:4> as fourth bank group address signals C1_BG<4>, C2_BG<4>,C3_BG<4> and C4_BG<4>.

The address generation circuit 5 may be synchronized with the first tofourth read bank selection signals ALR<1:4> and the first to fourthinternal read bank selection signals IALR<1:4> to output the first tofourth read column address signals RC<1:4> as the first bank groupaddress signals C1_BG<1>, C2_BG<1>, C3_BG<1> and C4_BG<1>. The addressgeneration circuit 5 may be synchronized with the first to fourth readbank selection signals ALR<1:4> and the first to fourth internal readbank selection signals IALR<1:4> to output the first to fourth readcolumn address signals RC<1:4> as the second bank group address signalsC1_BG<2>, C2_BG<2>, C3_BG<2> and C4_BG<2>. The address generationcircuit 5 may be synchronized with the first to fourth read bankselection signals ALR<1:4> and the first to fourth internal read bankselection signals IALR<1:4> to output the first to fourth read columnaddress signals RC<1:4> as the third bank group address signalsC1_BG<3>, C2_BG<3>, C3_BG<3> and C4_BG<3>. The address generationcircuit 5 may be synchronized with the first to fourth read bankselection signals ALR<1:4> and the first to fourth internal read bankselection signals IALR<1:4> to output the first to fourth read columnaddress signals RC<1:4> as the fourth bank group address signalsC1_BG<4>, C2_BG<4>, C3_BG<4> and C4_BG<4>.

The core circuit 6 may include first to fourth bank groups BK1, BK2, BK3and BK4.

The first bank group BK1 may perform the column operation to store dataDATA into memory cells (not shown) of a bank (not shown) selectedaccording to the first bank group address signals C1_BG<1>, C2_BG<1>,C3_BG<1> and C4_BG<1> during the write operation. The first bank groupBK1 may perform the column operation to output the data DATA stored inthe memory cells (not shown) of the bank (not shown) selected accordingto the first bank group address signals C1_BG<1>, C2_BG<1>, C3_BG<1> andC4_BG<1> during the read operation.

The second bank group BK2 may perform the column operation to store thedata DATA into memory cells (not shown) of a bank (not shown) selectedaccording to the second bank group address signals C1_BG<2>, C2_BG<2>,C3_BG<2> and C4_BG<2> during the write operation. The second bank groupBK2 may perform the column operation to output the data DATA stored inthe memory cells (not shown) of the bank (not shown) selected accordingto the second bank group address signals C1_BG<2>, C2_BG<2>, C3_BG<2>and C4_BG<2> during the read operation.

The third bank group BK3 may perform the column operation to store thedata DATA into memory cells (not shown) of a bank (not shown) selectedaccording to the third bank group address signals C1_BG<3>, C2_BG<3>,C3_BG<3> and C4_BG<3> during the write operation. The third bank groupBK3 may perform the column operation to output the data DATA stored inthe memory cells (not shown) of the bank (not shown) selected accordingto the third bank group address signals C1_BG<3>, C2_BG<3>, C3_BG<3> andC4_BG<3> during the read operation.

The fourth bank group BK4 may perform the column operation to store thedata DATA into memory cells (not shown) of a bank (not shown) selectedaccording to the fourth bank group address signals C1_BG<4>, C2_BG<4>,C3_BG<4> and C4_BG<4> during the write operation. The fourth bank groupBK4 may perform the column operation to output the data DATA stored inthe memory cells (not shown) of the bank (not shown) selected accordingto the fourth bank group address signals C1_BG<4>, C2_BG<4>, C3_BG<4>and C4_BG<4> during the read operation.

Referring to FIG. 2, the write control circuit 10 may include a writebank control circuit 11 and a write column control circuit 12.

The write bank control circuit 11 may include a first pipe controlcircuit 110, a first pipe circuit 120, a write delay circuit 130 and awrite bank selection signal generation circuit 140.

The first pipe control circuit 110 may be synchronized with the writeflag signal WTF and the internal write flag signal IWTF to generate afirst input control signal PIN1 and a first output control signal POUT1which are enabled, if the second write command pulse EWT2 is inputted tothe first pipe control circuit 110. The first pipe control circuit 110may generate the first input control signal PIN1 and the first outputcontrol signal POUT1 which are enabled in synchronization with the writeflag signal WTF if the second write command pulse EWT2 is inputted tothe first pipe control circuit 110. The first pipe control circuit 110may generate the first input control signal PIN1 and the first outputcontrol signal POUT1 which are enabled in synchronization with theinternal write flag signal IWTF if the second write command pulse EWT2is inputted to the first pipe control circuit 110.

The first pipe circuit 120 may be synchronized with the first inputcontrol signal PIN1 and the first output control signal POUT1 togenerate first and second write bank address signals BA_WT<1:2> from thefirst and second command/address signals CA<1:2>. The first pipe circuit120 may be synchronized with the first input control signal PIN1 tolatch the first and second command/address signals CA<1:2> and may thenbe synchronized with the first output control signal POUT1 to output thelatched signals of the first and second command/address signals CA<1:2>as the first and second write bank address signals BA_WT<1:2>. The firstand second command/address signals CA<1:2> may be set as signals forselecting the first to fourth bank groups BK1, BK2, BK3 and BK4 includedin the core circuit 6. The first and second command/address signalsCA<1:2> may be inputted to the first pipe circuit 120 in synchronizationwith a rising edge of the inverted internal clock signal ICLKB.

The write delay circuit 130 may delay the write column control pulseWTAYP and the internal write column control pulse IWTAYP by apredetermined period to generate a write latch pulse LPW and an internalwrite latch pulse ILPW. The write delay circuit 130 may delay the writecolumn control pulse WTAYP by the predetermined period to generate thewrite latch pulse LPW. The write delay circuit 130 may delay theinternal write column control pulse IWTAYP by the predetermined periodto generate the internal write latch pulse ILPW. A delay time of thewrite delay circuit 130 for delaying the write column control pulseWTAYP and the internal write column control pulse IWTAYP may be set tobe different according to the embodiments.

The write bank selection signal generation circuit 140 may besynchronized with the write latch pulse LPW to generate the first tofourth write bank selection signals ALW<1:4> from the first and secondwrite bank address signals BA_WT<1:2> and may be synchronized with theinternal write latch pulse ILPW to generate the first to fourth internalwrite bank selection signals IALW<1:4> from the first and second writebank address signals BA_WT<1:2>. The write bank selection signalgeneration circuit 140 may be synchronized with the write latch pulseLPW to generate the first to fourth write bank selection signalsALW<1:4>, one of which is selectively enabled according to a logic levelcombination of the first and second write bank address signalsBA_WT<1:2>. The write bank selection signal generation circuit 140 maybe synchronized with the internal write latch pulse ILPW to generate thefirst to fourth internal write bank selection signals IALW<1:4>, one ofwhich is selectively enabled according to a logic level combination ofthe first and second write bank address signals BA_WT<1:2>.

The write bank control circuit 11 may latch the first and secondcommand/address signals CA<1:2> in synchronization with the write flagsignal WTF and the internal write flag signal IWTF if the second writecommand pulse EWT2 is enabled to perform the write operation. The writebank control circuit 11 may be synchronized with the write columncontrol pulse WTAYP and the internal write column control pulse IWTAYPto generate the first to fourth write bank selection signals ALW<1:4>and the first to fourth internal write bank selection signals IALW<1:4>from the latched signals of the first and second command/address signalsCA<1:2>.

The write column control circuit 12 may include a second pipe controlcircuit 150 and a second pipe circuit 160.

The second pipe control circuit 150 may generate a second input controlsignal PIN2 and a second output control signal POUT2 which are enabledin synchronization with the write column control pulse WTAYP and theinternal write column control pulse IWTAYP if the second write commandpulse EWT2 is inputted to the second pipe control circuit 150. Thesecond pipe control circuit 150 may generate the second input controlsignal PIN2 and the second output control signal POUT2 which are enabledin synchronization with the write column control pulse WTAYP if thesecond write command pulse EWT2 is inputted to the second pipe controlcircuit 150. The second pipe control circuit 150 may generate the secondinput control signal PIN2 and the second output control signal POUT2which are enabled in synchronization with the internal write columncontrol pulse IWTAYP if the second write command pulse EWT2 is inputtedto the second pipe control circuit 150.

The second pipe circuit 160 may be synchronized with the second inputcontrol signal PIN2 and the second output control signal POUT2 togenerate the first to fourth write column address signals WC<1:4> fromthe third to sixth command/address signals CA<3:6>. The second pipecircuit 160 may be synchronized with the second input control signalPIN2 to latch the third to sixth command/address signals CA<3:6> and maythen be synchronized with the second output control signal POUT2 tooutput the latched signals of the third to sixth command/address signalsCA<3:6> as the first to fourth write column address signals WC<1:4>. Thethird to sixth command/address signals CA<3:6> may be set as signals forselecting memory cells (not shown) included in the first to fourth bankgroups BK1, BK2, BK3 and BK4. The third to sixth command/address signalsCA<3:6> may be inputted to the second pipe circuit 160 insynchronization with a rising edge of the inverted internal clock signalICLKB.

The write column control circuit 12 may generate the first to fourthwrite column address signals WC<1:4> from the third to sixthcommand/address signals CA<3:6> in synchronization with the write columncontrol pulse WTAYP and the internal write column control pulse IWTAYPif the second write command pulse EWT2 is inputted to the write columncontrol circuit 12.

The write control circuit 10 may generate the first to fourth write bankselection signals ALW<1:4> and the first to fourth internal write bankselection signals IALW<1:4> from the first and second command/addresssignals CA<1:2> in synchronization with the write flag signal WTF andthe internal write flag signal IWTF. The write control circuit 10 maygenerate the first to fourth write column address signals WC<1:4> fromthe third to sixth command/address signals CA<3:6> in synchronizationwith the write column control pulse WTAYP and the internal write columncontrol pulse IWTAYP.

Referring to FIG. 3, the write bank selection signal generation circuit140 may include a first write bank selection signal generation circuit141, a second write bank selection signal generation circuit 142, athird write bank selection signal generation circuit 143 and a fourthwrite bank selection signal generation circuit 144.

The first write bank selection signal generation circuit 141 maygenerate the first write bank selection signal ALW<1> which is enabledin synchronization with the write latch pulse LPW if the first andsecond write bank address signals BA_WT<1:2> have a first logic levelcombination. The first write bank selection signal generation circuit141 may generate the first internal write bank selection signal IALW<1>which is enabled in synchronization with the internal write latch pulseILPW if the first and second write bank address signals BA_WT<1:2> havethe first logic level combination. The first logic level combination ofthe first and second write bank address signals BA_WT<1:2> means thatthe first write bank address signal BA_WT<1> has a logic “low” level andthe second write bank address signal BA_WT<2> has a logic “low” level.

The second write bank selection signal generation circuit 142 maygenerate the second write bank selection signal ALW<2> which is enabledin synchronization with the write latch pulse LPW if the first andsecond write bank address signals BA_WT<1:2> have a second logic levelcombination. The second write bank selection signal generation circuit142 may generate the second internal write bank selection signal IALW<2>which is enabled in synchronization with the internal write latch pulseILPW if the first and second write bank address signals BA_WT<1:2> havethe second logic level combination. The second logic level combinationof the first and second write bank address signals BA_WT<1:2> means thatthe first write bank address signal BA_WT<1> has a logic “high” leveland the second write bank address signal BA_WT<2> has a logic “low”level.

The third write bank selection signal generation circuit 143 maygenerate the third write bank selection signal ALW<3> which is enabledin synchronization with the write latch pulse LPW if the first andsecond write bank address signals BA_WT<1:2> have a third logic levelcombination. The third write bank selection signal generation circuit143 may generate the third internal write bank selection signal IALW<3>which is enabled in synchronization with the internal write latch pulseILPW if the first and second write bank address signals BA_WT<1:2> havethe third logic level combination. The third logic level combination ofthe first and second write bank address signals BA_WT<1:2> means thatthe first write bank address signal BA_WT<1> has a logic “low” level andthe second write bank address signal BA_WT<2> has a logic “high” level.

The fourth write bank selection signal generation circuit 144 maygenerate the fourth write bank selection signal ALW<4> which is enabledin synchronization with the write latch pulse LPW if the first andsecond write bank address signals BA_WT<1:2> have a fourth logic levelcombination. The fourth write bank selection signal generation circuit144 may generate the fourth internal write bank selection signal IALW<4>which is enabled in synchronization with the internal write latch pulseILPW if the first and second write bank address signals BA_WT<1:2> havethe fourth logic level combination. The fourth logic level combinationof the first and second write bank address signals BA_WT<1:2> means thatthe first write bank address signal BA_WT<1> has a logic “high” leveland the second write bank address signal BA_WT<2> has a logic “high”level.

Referring to FIG. 4, the first write bank selection signal generationcircuit 141 may include a first pulse generation circuit 1100 and asecond pulse generation circuit 1200.

The first pulse generation circuit 1100 may generate the first writebank selection signal ALW<1> which is enabled to have a logic “high”level in synchronization with the write latch pulse LPW if the first andsecond write bank address signals BA_WT<1:2> have the first logic levelcombination. The first pulse generation circuit 1100 may generate thefirst write bank selection signal ALW<1> which is enabled to have alogic “high” level in synchronization with the write latch pulse LPW ifthe first write bank address signal BA_WT<1> has a logic “low” level andthe second write bank address signal BA_WT<2> has a logic “low” level.In an embodiment, the first pulse generation circuit 1100 may performinversion, NAND operations, and perform a latching operation, and mayinclude a combination of inverters, NAND logic gates, and a flip flopF/F as illustrated in FIG. 4.

The second pulse generation circuit 1200 may generate the first internalwrite bank selection signal IALW<1> which is enabled to have a logic“high” level in synchronization with the internal write latch pulse ILPWif the first and second write bank address signals BA_WT<1:2> have thefirst logic level combination. The second pulse generation circuit 1200may generate the first internal write bank selection signal IALW<1>which is enabled to have a logic “high” level in synchronization withthe internal write latch pulse ILPW if the first write bank addresssignal BA_WT<1> has a logic “low” level and the second write bankaddress signal BA_WT<2> has a logic “low” level. In an embodiment, thesecond pulse generation circuit 1200 may perform inversion, NANDoperations, and perform a latching operation, and may include acombination of inverters, NAND logic gates, and a flip flop F/F asillustrated in FIG. 4.

Referring to FIG. 5, the second write bank selection signal generationcircuit 142 may include a third pulse generation circuit 1300 and afourth pulse generation circuit 1400.

The third pulse generation circuit 1300 may generate the second writebank selection signal ALW<2> which is enabled to have a logic “high”level in synchronization with the write latch pulse LPW if the first andsecond write bank address signals BA_WT<1:2> have the second logic levelcombination. The third pulse generation circuit 1300 may generate thesecond write bank selection signal ALW<2> which is enabled to have alogic “high” level in synchronization with the write latch pulse LPW ifthe first write bank address signal BA_WT<1> has a logic “high” leveland the second write bank address signal BA_WT<2> has a logic “low”level. In an embodiment, the third pulse generation circuit 1300 mayperform inversion, NAND operations, and perform a latching operation,and may include a combination of inverters, NAND logic gates, and a flipflop F/F as illustrated in FIG. 5.

The fourth pulse generation circuit 1400 may generate the secondinternal write bank selection signal IALW<2> which is enabled to have alogic “high” level in synchronization with the internal write latchpulse ILPW if the first and second write bank address signals BA_WT<1:2>have the second logic level combination. The fourth pulse generationcircuit 1400 may generate the second internal write bank selectionsignal IALW<2> which is enabled to have a logic “high” level insynchronization with the internal write latch pulse ILPW if the firstwrite bank address signal BA_WT<1> has a logic “high” level and thesecond write bank address signal BA_WT<2> has a logic “low” level. In anembodiment, the fourth pulse generation circuit 1400 may performinversion, NAND operations, and perform a latching operation, and mayinclude a combination of inverters, NAND logic gates, and a flip flopF/F as illustrated in FIG. 5.

Referring to FIG. 6, the third write bank selection signal generationcircuit 143 may include a fifth pulse generation circuit 1500 and asixth pulse generation circuit 1600.

The fifth pulse generation circuit 1500 may generate the third writebank selection signal ALW<3> which is enabled to have a logic “high”level in synchronization with the write latch pulse LPW if the first andsecond write bank address signals BA_WT<1:2> have the third logic levelcombination. The fifth pulse generation circuit 1500 may generate thethird write bank selection signal ALW<3> which is enabled to have alogic “high” level in synchronization with the write latch pulse LPW ifthe first write bank address signal BA_WT<1> has a logic “low” level andthe second write bank address signal BA_WT<2> has a logic “high” level.In an embodiment, the fifth pulse generation circuit 1500 may performinversion, NAND operations, and perform a latching operation, and mayinclude a combination of inverters, NAND logic gates, and a flip flopF/F as illustrated in FIG. 6.

The sixth pulse generation circuit 1600 may generate the third internalwrite bank selection signal IALW<3> which is enabled to have a logic“high” level in synchronization with the internal write latch pulse ILPWif the first and second write bank address signals BA_WT<1:2> have thethird logic level combination. The sixth pulse generation circuit 1600may generate the third internal write bank selection signal IALW<3>which is enabled to have a logic “high” level in synchronization withthe internal write latch pulse ILPW if the first write bank addresssignal BA_WT<1> has a logic “low” level and the second write bankaddress signal BA_WT<2> has a logic “high” level. In an embodiment, thesixth pulse generation circuit 1600 may perform inversion, NANDoperations, and perform a latching operation, and may include acombination of inverters, NAND logic gates, and a flip flop F/F asillustrated in FIG. 6.

Referring to FIG. 7, the fourth write bank selection signal generationcircuit 144 may include a seventh pulse generation circuit 1700 and aneighth pulse generation circuit 1800.

The seventh pulse generation circuit 1700 may generate the fourth writebank selection signal ALW<4> which is enabled to have a logic “high”level in synchronization with the write latch pulse LPW if the first andsecond write bank address signals BA_WT<1:2> have the fourth logic levelcombination. The seventh pulse generation circuit 1700 may generate thefourth write bank selection signal ALW<4> which is enabled to have alogic “high” level in synchronization with the write latch pulse LPW ifthe first write bank address signal BA_WT<1> has a logic “high” leveland the second write bank address signal BA_WT<2> has a logic “high”level. In an embodiment, the seventh pulse generation circuit 1700 mayperform inversion, NAND operations, and perform a latching operation,and may include a combination of inverters, NAND logic gates, and a flipflop F/F as illustrated in FIG. 7.

The eighth pulse generation circuit 1800 may generate the fourthinternal write bank selection signal IALW<4> which is enabled to have alogic “high” level in synchronization with the internal write latchpulse ILPW if the first and second write bank address signals BA_WT<1:2>have the fourth logic level combination. The eighth pulse generationcircuit 1800 may generate the fourth internal write bank selectionsignal IALW<4> which is enabled to have a logic “high” level insynchronization with the internal write latch pulse ILPW if the firstwrite bank address signal BA_WT<1> has a logic “high” level and thesecond write bank address signal BA_WT<2> has a logic “high” level. Inan embodiment, the eighth pulse generation circuit 1800 may performinversion, NAND operations, and perform a latching operation, and mayinclude a combination of inverters, NAND logic gates, and a flip flopF/F as illustrated in FIG. 7.

Referring to FIG. 8, the read control circuit 20 may include a read bankcontrol circuit 21 and a latch circuit 22.

The read bank control circuit 21 may include a third pipe controlcircuit 210, a third pipe circuit 220, a read delay circuit 230 and aread bank selection signal generation circuit 240.

The third pipe control circuit 210 may generate a third input controlsignal PIN3 and a third output control signal POUT3 which is enabled insynchronization with the read flag signal RDF and the internal read flagsignal IRDF if the second read command pulse ERD2 is inputted to thethird pipe control circuit 210. The third pipe control circuit 210 maygenerate the third input control signal PIN3 and the third outputcontrol signal POUT3 which are enabled in synchronization with the readflag signal RDF if the second read command pulse ERD2 is inputted to thethird pipe control circuit 210. The third pipe control circuit 210 maygenerate the third input control signal PIN3 and the third outputcontrol signal POUT3 which are enabled in synchronization with theinternal read flag signal IRDF if the second read command pulse ERD2 isinputted to the third pipe control circuit 210.

The third pipe circuit 220 may be synchronized with the third inputcontrol signal PIN3 and the third output control signal POUT3 togenerate first and second read bank address signals BA_RD<1:2> from thefirst and second command/address signals CA<1:2>. The third pipe circuit220 may be synchronized with the third input control signal PIN3 tolatch the first and second command/address signals CA<1:2> and may thenbe synchronized with the third output control signal POUT3 to output thelatched signals of the first and second command/address signals CA<1:2>as the first and second read bank address signals BA_RD<1:2>. The firstand second command/address signals CA<1:2> may be inputted to the thirdpipe circuit 220 in synchronization with a rising edge of the invertedinternal clock signal ICLKB.

The read delay circuit 230 may delay the read column control pulse RDAYPand the internal read column control pulse IRDAYP by a predeterminedperiod to generate a read latch pulse LPR and an internal read latchpulse ILPR. The read delay circuit 230 may delay the read column controlpulse RDAYP by the predetermined period to generate the read latch pulseLPR. The read delay circuit 230 may delay the internal read columncontrol pulse IRDAYP by the predetermined period to generate theinternal read latch pulse ILPR. A delay time of the read delay circuit230 for delaying the read column control pulse RDAYP and the internalread column control pulse IRDAYP may be set to be different according tothe embodiments.

The read bank selection signal generation circuit 240 may besynchronized with the read latch pulse LPR to generate the first tofourth read bank selection signals ALR<1:4> from the first and secondread bank address signals BA_RD<1:2> and may be synchronized with theinternal read latch pulse ILPR to generate the first to fourth internalread bank selection signals IALR<1:4> from the first and second readbank address signals BA_RD<1:2>. The read bank selection signalgeneration circuit 240 may be synchronized with the read latch pulse LPRto generate the first to fourth read bank selection signals ALR<1:4>,one of which is selectively enabled according to a logic levelcombination of the first and second read bank address signalsBA_RD<1:2>. The read bank selection signal generation circuit 240 may besynchronized with the internal read latch pulse ILPR to generate thefirst to fourth internal read bank selection signals IALR<1:4>, one ofwhich is selectively enabled according to a logic level combination ofthe first and second read bank address signals BA_RD<1:2>.

The read bank control circuit 21 may latch the first and secondcommand/address signals CA<1:2> in synchronization with the read flagsignal RDF and the internal read flag signal IRDF if the second readcommand pulse ERD2 is enabled to perform the read operation. The readbank control circuit 21 may be synchronized with the read column controlpulse RDAYP and the internal read column control pulse IRDAYP togenerate the first to fourth read bank selection signals ALR<1:4> andthe first to fourth internal read bank selection signals IALR<1:4> fromthe latched signals of the first and second command/address signalsCA<1:2>.

The latch circuit 22 may generate the first to fourth read columnaddress signals RC<1:4> from the third to sixth command/address signalsCA<3:6> in synchronization with the read column control pulse RDAYP ifthe second read command pulse ERD2 is inputted to the latch circuit 22.If the second read command pulse ERD2 is inputted to the latch circuit22, the latch circuit 22 may latch the third to sixth command/addresssignals CA<3:6> in synchronization with the read column control pulseRDAYP and may generate the first to fourth read column address signalsRC<1:4> from the latched signals of the third to sixth command/addresssignals CA<3:6>. The third to sixth command/address signals CA<3:6> maybe inputted to the latch circuit 22 in synchronization with a risingedge of the inverted internal clock signal ICLKB.

The read control circuit 20 may generate the first to fourth read bankselection signals ALR<1:4> and the first to fourth internal read bankselection signals IALR<1:4> from the first and second command/addresssignals CA<1:2> in synchronization with the read flag signal RDF and theinternal read flag signal IRDF. The read control circuit 20 may generatethe first to fourth read column address signals RC<1:4> from the thirdto sixth command/address signals CA<3:6> in synchronization with theread column control pulse RDAYP.

Referring to FIG. 9, the read bank selection signal generation circuit240 may include a first read bank selection signal generation circuit241, a second read bank selection signal generation circuit 242, a thirdread bank selection signal generation circuit 243 and a fourth read bankselection signal generation circuit 244.

The first read bank selection signal generation circuit 241 may generatethe first read bank selection signal ALR<1> which is enabled insynchronization with the read latch pulse LPR if the first and secondread bank address signals BA_RD<1:2> have a first logic levelcombination. The first read bank selection signal generation circuit 241may generate the first internal read bank selection signal IALR<1> whichis enabled in synchronization with the internal read latch pulse ILPR ifthe first and second read bank address signals BA_RD<1:2> have the firstlogic level combination. The first logic level combination of the firstand second read bank address signals BA_RD<1:2> means that the firstread bank address signal BA_RD<1> has a logic “low” level and the secondread bank address signal BA_RD<2> has a logic “low” level.

The second read bank selection signal generation circuit 242 maygenerate the second read bank selection signal ALR<2> which is enabledin synchronization with the read latch pulse LPR if the first and secondread bank address signals BA_RD<1:2> have a second logic levelcombination. The second read bank selection signal generation circuit242 may generate the second internal read bank selection signal IALR<2>which is enabled in synchronization with the internal read latch pulseILPR if the first and second read bank address signals BA_RD<1:2> havethe second logic level combination. The second logic level combinationof the first and second read bank address signals BA_RD<1:2> means thatthe first read bank address signal BA_RD<1> has a logic “high” level andthe second read bank address signal BA_RD<2> has a logic “low” level.

The third read bank selection signal generation circuit 243 may generatethe third read bank selection signal ALR<3> which is enabled insynchronization with the read latch pulse LPR if the first and secondread bank address signals BA_RD<1:2> have a third logic levelcombination. The third read bank selection signal generation circuit 243may generate the third internal read bank selection signal IALR<3> whichis enabled in synchronization with the internal read latch pulse ILPR ifthe first and second read bank address signals BA_RD<1:2> have the thirdlogic level combination. The third logic level combination of the firstand second read bank address signals BA_RD<1:2> means that the firstread bank address signal BA_RD<1> has a logic “low” level and the secondread bank address signal BA_RD<2> has a logic “high” level.

The fourth read bank selection signal generation circuit 244 maygenerate the fourth read bank selection signal ALR<4> which is enabledin synchronization with the read latch pulse LPR if the first and secondread bank address signals BA_RD<1:2> have a fourth logic levelcombination. The fourth read bank selection signal generation circuit244 may generate the fourth internal read bank selection signal IALR<4>which is enabled in synchronization with the internal read latch pulseILPR if the first and second read bank address signals BA_RD<1:2> havethe fourth logic level combination. The fourth logic level combinationof the first and second read bank address signals BA_RD<1:2> means thatthe first read bank address signal BA_RD<1> has a logic “high” level andthe second read bank address signal BA_RD<2> has a logic “high” level.

Referring to FIG. 10, the first read bank selection signal generationcircuit 241 may include a ninth pulse generation circuit 2100 and atenth pulse generation circuit 2200.

The ninth pulse generation circuit 2100 may generate the first read bankselection signal ALR<1> which is enabled to have a logic “high” level insynchronization with the read latch pulse LPR if the first and secondread bank address signals BA_RD<1:2> have the first logic levelcombination. The ninth pulse generation circuit 2100 may generate thefirst read bank selection signal ALR<1> which is enabled to have a logic“high” level in synchronization with the read latch pulse LPR if thefirst read bank address signal BA_RD<1> has a logic “low” level and thesecond read bank address signal BA_RD<2> has a logic “low” level. In anembodiment, the ninth pulse generation circuit 2100 may performinversion, NAND operations, and perform a latching operation, and mayinclude a combination of inverters, NAND logic gates, and a flip flopF/F as illustrated in FIG. 10.

The tenth pulse generation circuit 2200 may generate the first internalread bank selection signal IALR<1> which is enabled to have a logic“high” level in synchronization with the internal read latch pulse ILPRif the first and second read bank address signals BA_RD<1:2> have thefirst logic level combination. The tenth pulse generation circuit 2200may generate the first internal read bank selection signal IALR<1> whichis enabled to have a logic “high” level in synchronization with theinternal read latch pulse ILPR if the first read bank address signalBA_RD<1> has a logic “low” level and the second read bank address signalBA_RD<2> has a logic “low” level. In an embodiment, the tenth pulsegeneration circuit 2200 may perform inversion, NAND operations, andperform a latching operation, and may include a combination ofinverters, NAND logic gates, and a flip flop F/F as illustrated in FIG.10.

Referring to FIG. 11, the second read bank selection signal generationcircuit 242 may include an eleventh pulse generation circuit 2300 and atwelfth pulse generation circuit 2400.

The eleventh pulse generation circuit 2300 may generate the second readbank selection signal ALR<2> which is enabled to have a logic “high”level in synchronization with the read latch pulse LPR if the first andsecond read bank address signals BA_RD<1:2> have the second logic levelcombination. The eleventh pulse generation circuit 2300 may generate thesecond read bank selection signal ALR<2> which is enabled to have alogic “high” level in synchronization with the read latch pulse LPR ifthe first read bank address signal BA_RD<1> has a logic “high” level andthe second read bank address signal BA_RD<2> has a logic “low” level. Inan embodiment, the eleventh pulse generation circuit 2300 may performinversion, NAND operations, and perform a latching operation, and mayinclude a combination of inverters, NAND logic gates, and a flip flopF/F as illustrated in FIG. 11.

The twelfth pulse generation circuit 2400 may generate the secondinternal read bank selection signal IALR<2> which is enabled to have alogic “high” level in synchronization with the internal read latch pulseILPR if the first and second read bank address signals BA_RD<1:2> havethe second logic level combination. The twelfth pulse generation circuit2400 may generate the second internal read bank selection signal IALR<2>which is enabled to have a logic “high” level in synchronization withthe internal read latch pulse ILPR if the first read bank address signalBA_RD<1> has a logic “high” level and the second read bank addresssignal BA_RD<2> has a logic “low” level. In an embodiment, the twelfthpulse generation circuit 2400 may perform inversion, NAND operations,and perform a latching operation, and may include a combination ofinverters, NAND logic gates, and a flip flop F/F as illustrated in FIG.11.

Referring to FIG. 12, the third read bank selection signal generationcircuit 243 may include a thirteenth pulse generation circuit 2500 and afourteenth pulse generation circuit 2600.

The thirteenth pulse generation circuit 2500 may generate the third readbank selection signal ALR<3> which is enabled to have a logic “high”level in synchronization with the read latch pulse LPR if the first andsecond read bank address signals BA_RD<1:2> have the third logic levelcombination. The thirteenth pulse generation circuit 2500 may generatethe third read bank selection signal ALR<3> which is enabled to have alogic “high” level in synchronization with the read latch pulse LPR ifthe first read bank address signal BA_RD<1> has a logic “low” level andthe second read bank address signal BA_RD<2> has a logic “high” level.In an embodiment, the thirteenth pulse generation circuit 2500 mayperform inversion, NAND operations, and perform a latching operation,and may include a combination of inverters, NAND logic gates, and a flipflop F/F as illustrated in FIG. 12.

The fourteenth pulse generation circuit 2600 may generate the thirdinternal read bank selection signal IALR<3> which is enabled to have alogic “high” level in synchronization with the internal read latch pulseILPR if the first and second read bank address signals BA_RD<1:2> havethe third logic level combination. The fourteenth pulse generationcircuit 2600 may generate the third internal read bank selection signalIALR<3> which is enabled to have a logic “high” level in synchronizationwith the internal read latch pulse ILPR if the first read bank addresssignals BA_RD<1> has a logic “low” level and the second read bankaddress signals BA_RD<2> has a logic “high” level. In an embodiment, thefourteenth pulse generation circuit 2600 may perform inversion, NANDoperations, and perform a latching operation, and may include acombination of inverters, NAND logic gates, and a flip flop F/F asillustrated in FIG. 12.

Referring to FIG. 13, the fourth read bank selection signal generationcircuit 244 may include a fifteenth pulse generation circuit 2700 and asixteenth pulse generation circuit 2800.

The fifteenth pulse generation circuit 2700 may generate the fourth readbank selection signal ALR<4> which is enabled to have a logic “high”level in synchronization with the read latch pulse LPR if the first andsecond read bank address signals BA_RD<1:2> have the fourth logic levelcombination. The fifteenth pulse generation circuit 2700 may generatethe fourth read bank selection signal ALR<4> which is enabled to have alogic “high” level in synchronization with the read latch pulse LPR ifthe first read bank address signals BA_RD<1> has a logic “high” leveland the second read bank address signals BA_RD<2> has a logic “high”level. In an embodiment, the fifteenth pulse generation circuit 2700 mayperform inversion, NAND operations, and perform a latching operation,and may include a combination of inverters, NAND logic gates, and a flipflop F/F as illustrated in FIG. 13.

The sixteenth pulse generation circuit 2800 may generate the fourthinternal read bank selection signal IALR<4> which is enabled to have alogic “high” level in synchronization with the internal read latch pulseILPR if the first and second read bank address signals BA_RD<1:2> havethe fourth logic level combination. The sixteenth pulse generationcircuit 2800 may generate the fourth internal read bank selection signalIALR<4> which is enabled to have a logic “high” level in synchronizationwith the internal read latch pulse ILPR if the first read bank addresssignals BA_RD<1> has a logic “high” level and the second read bankaddress signals BA_RD<2> has a logic “high” level. In an embodiment, thesixteenth pulse generation circuit 2800 may perform inversion, NANDoperations, and perform a latching operation, and may include acombination of inverters, NAND logic gates, and a flip flop F/F asillustrated in FIG. 13.

Referring to FIG. 14, the address generation circuit 5 may include afirst address generation circuit 51, a second address generation circuit52, a third address generation circuit 53 and a fourth addressgeneration circuit 54.

The first address generation circuit 51 may be synchronized with thefirst to fourth write bank selection signals ALW<1:4> and the first tofourth internal write bank selection signals IALW<1:4> to output thefirst write column address signal WC<1> as one of the first to fourthbank group address signals C1_BG<1:4>. The first address generationcircuit 51 may be synchronized with the first to fourth read bankselection signals ALR<1:4> and the first to fourth internal read bankselection signals IALR<1:4> to output the first read column addresssignal RC<1> as one of the first to fourth bank group address signalsC1_BG<1:4>.

The second address generation circuit 52 may be synchronized with thefirst to fourth write bank selection signals ALW<1:4> to output thesecond write column address signal WC<2> as one of the first to fourthbank group address signals C2_BG<1:4>. The second address generationcircuit 52 may be synchronized with the first to fourth read bankselection signals ALR<1:4> to output the second read column addresssignal RC<2> as one of the first to fourth bank group address signalsC2_BG<1:4>.

The third address generation circuit 53 may be synchronized with thefirst to fourth write bank selection signals ALW<1:4> to output thethird write column address signal WC<3> as one of the first to fourthbank group address signals C3_BG<1:4>. The third address generationcircuit 53 may be synchronized with the first to fourth read bankselection signals ALR<1:4> to output the third read column addresssignal RC<3> as one of the first to fourth bank group address signalsC3_BG<1:4>.

The fourth address generation circuit 54 may be synchronized with thefirst to fourth write bank selection signals ALW<1:4> to output thefourth write column address signal WC<4> as one of the first to fourthbank group address signals C4_BG<1:4>. The fourth address generationcircuit 54 may be synchronized with the first to fourth read bankselection signals ALR<1:4> to output the fourth read column addresssignal RC<4> as one of the first to fourth bank group address signalsC4_BG<1:4>.

Referring to FIG. 15, the first address generation circuit 51 mayinclude a first address output circuit 510, a second address outputcircuit 520, a third address output circuit 530 and a fourth addressoutput circuit 540.

The first address output circuit 510 may buffer the first write columnaddress signal WC<1> to output the buffered signal of the first writecolumn address signal WC<1> as the first bit C1_BG<1> of the first bankgroup address signals C1_BG<1>, C2_BG<1>, C3_BG<1> and C4_BG<1>, if thefirst write bank selection signal ALW<1> is enabled. The first addressoutput circuit 510 may inversely buffer the first write column addresssignal WC<1> to output the inversely buffered signal of the first writecolumn address signal WC<1> as the first bit C1_BG<1> of the first bankgroup address signals C1_BG<1>, C2_BG<1>, C3_BG<1> and C4_BG<1>, if thefirst internal write bank selection signal IALW<1> is enabled. The firstaddress output circuit 510 may buffer the first read column addresssignal RC<1> to output the buffered signal of the first read columnaddress signal RC<1> as the first bit C1_BG<1> of the first bank groupaddress signals C1_BG<1>, C2_BG<1>, C3_BG<1> and C4_BG<1>, if the firstread bank selection signal ALR<1> is enabled. The first address outputcircuit 510 may inversely buffer the first read column address signalRC<1> to output the inversely buffered signal of the first read columnaddress signal RC<1> as the first bit C1_BG<1> of the first bank groupaddress signals C1_BG<1>, C2_BG<1>, C3_BG<1> and C4_BG<1>, if the firstinternal read bank selection signal IALR<1> is enabled.

The second address output circuit 520 may buffer the first write columnaddress signal WC<1> to output the buffered signal of the first writecolumn address signal WC<1> as the first bit C1_BG<2> of the second bankgroup address signals C1_BG<2>, C2_BG<2>, C3_BG<2> and C4_BG<2>, if thesecond write bank selection signal ALW<2> is enabled. The second addressoutput circuit 520 may inversely buffer the first write column addresssignal WC<1> to output the inversely buffered signal of the first writecolumn address signal WC<1> as the first bit C1_BG<2> of the second bankgroup address signals C1_BG<2>, C2_BG<2>, C3_BG<2> and C4_BG<2>, if thesecond internal write bank selection signal IALW<2> is enabled. Thesecond address output circuit 520 may buffer the first read columnaddress signal RC<1> to output the buffered signal of the first readcolumn address signal RC<1> as the first bit C1_BG<2> of the second bankgroup address signals C1_BG<2>, C2_BG<2>, C3_BG<2> and C4_BG<2>, if thesecond read bank selection signal ALR<2> is enabled. The second addressoutput circuit 520 may inversely buffer the first read column addresssignal RC<1> to output the inversely buffered signal of the first readcolumn address signal RC<1> as the first bit C1_BG<2> of the second bankgroup address signals C1_BG<2>, C2_BG<2>, C3_BG<2> and C4_BG<2>, if thesecond internal read bank selection signal IALR<2> is enabled.

The third address output circuit 530 may buffer the first write columnaddress signal WC<1> to output the buffered signal of the first writecolumn address signal WC<1> as the first bit C1_BG<3> of the third bankgroup address signals C1_BG<3>, C2_BG<3>, C3_BG<3> and C4_BG<3>, if thethird write bank selection signal ALW<3> is enabled. The third addressoutput circuit 530 may inversely buffer the first write column addresssignal WC<1> to output the inversely buffered signal of the first writecolumn address signal WC<1> as the first bit C1_BG<3> of the third bankgroup address signals C1_BG<3>, C2_BG<3>, C3_BG<3> and C4_BG<3>, if thethird internal write bank selection signal IALW<3> is enabled. The thirdaddress output circuit 530 may buffer the first read column addresssignal RC<1> to output the buffered signal of the first read columnaddress signal RC<1> as the first bit C1_BG<3> of the third bank groupaddress signals C1_BG<3>, C2_BG<3>, C3_BG<3> and C4_BG<3>, if the thirdread bank selection signal ALR<3> is enabled. The third address outputcircuit 530 may inversely buffer the first read column address signalRC<1> to output the inversely buffered signal of the first read columnaddress signal RC<1> as the first bit C1_BG<3> of the third bank groupaddress signals C1_BG<3>, C2_BG<3>, C3_BG<3> and C4_BG<3>, if the thirdinternal read bank selection signal IALR<3> is enabled.

The fourth address output circuit 540 may buffer the first write columnaddress signal WC<1> to output the buffered signal of the first writecolumn address signal WC<1> as the first bit C1_BG<4> of the fourth bankgroup address signals C1_BG<4>, C2_BG<4>, C3_BG<4> and C4_BG<4>, if thefourth write bank selection signal ALW<4> is enabled. The fourth addressoutput circuit 540 may inversely buffer the first write column addresssignal WC<1> to output the inversely buffered signal of the first writecolumn address signal WC<1> as the first bit C1_BG<4> of the fourth bankgroup address signals C1_BG<4>, C2_BG<4>, C3_BG<4> and C4_BG<4>, if thefourth internal write bank selection signal IALW<4> is enabled. Thefourth address output circuit 540 may buffer the first read columnaddress signal RC<1> to output the buffered signal of the first readcolumn address signal RC<1> as the first bit C1_BG<4> of the fourth bankgroup address signals C1_BG<4>, C2_BG<4>, C3_BG<4> and C4_BG<4>, if thefourth read bank selection signal ALR<4> is enabled. The fourth addressoutput circuit 540 may inversely buffer the first read column addresssignal RC<1> to output the inversely buffered signal of the first readcolumn address signal RC<1> as the first bit C1_BG<4> of the fourth bankgroup address signals C1_BG<4>, C2_BG<4>, C3_BG<4> and C4_BG<4>, if thefourth internal read bank selection signal IALR<4> is enabled.

Referring to FIG. 16, the first address output circuit 510 may include afirst signal transmission circuit 5100, a second signal transmissioncircuit 5200 and a first buffer circuit 5300.

The first signal transmission circuit 5100 may receive the first writecolumn address signal WC<1> if the first write bank selection signalALW<1> has a logic “low” level. The first signal transmission circuit5100 may latch the first write column address signal WC<1> inputted tothe first signal transmission circuit 5100 and may buffer the latchedsignal of the first write column address signal WC<1> to generate afirst transmission signal TS<1> if the first write bank selection signalALW<1> has a logic “high” level. The first signal transmission circuit5100 may buffer the first transmission signal TS<1> to generate a firstpre-transmission signal PTS<1> if the first internal write bankselection signal IALW<1> has a logic “high” level and may inverselybuffer the first pre-transmission signal PTS<1> to generate the firsttransmission signal TS<1> regardless of the first internal write bankselection signal IALW<1>. The first signal transmission circuit 5100 maygenerate the first pre-transmission signal PTS<1> which is initializedto have a logic “low” level if a reset signal RST is enabled to have alogic “low” level and the first internal write bank selection signalIALW<1> has a logic “high” level. The reset signal RST may be set as asignal which is enabled to perform an initialization operation of thesemiconductor device. In an embodiment, the first signal transmissioncircuit 5100 may also receive a complementary first write bank selectionsignal ALWB<1> and a complementary first internal write bank selectionsignal IALWB<1>.

The second signal transmission circuit 5200 may receive the first readcolumn address signal RC<1> if the first read bank selection signalALR<1> has a logic “low” level. The second signal transmission circuit5200 may latch the first read column address signal RC<1> inputted tothe second signal transmission circuit 5200 and may inversely buffer thelatched signal of the first read column address signal RC<1> to generatethe first pre-transmission signal PTS<1> if the first read bankselection signal ALR<1> has a logic “high” level. The second signaltransmission circuit 5200 may invert the first pre-transmission signalPTS<1> if the first internal read bank selection signal IALR<1> has alogic “high” level. The second signal transmission circuit 5200 maygenerate the first pre-transmission signal PTS<1> which is initializedto have a logic “low” level if the reset signal RST is enabled to have alogic “low” level. In an embodiment, the second signal transmissioncircuit 5200 may also receive a complementary first read bank selectionsignal ALRB<1> and a complementary first internal read bank selectionsignal IALRB<1>.

The buffer circuit 5300 may buffer the first transmission signal TS<1>to output the buffered signal of the first transmission signal TS<1> asthe first bit C1_BG<1> of the first bank group address signals C1_BG<1>,C2_BG<1>, C3_BG<1> and C4_BG<1>.

Each of the second to fourth address output circuits 520, 530 and 540illustrated in FIG. 15 may be realized using substantially the samecircuit as the first output circuit 510 illustrated in FIG. 16 exceptits input/output (I/O) signals. Thus, descriptions of the second tofourth address output circuits 520, 530 and 540 will be omittedhereinafter.

Referring to FIG. 17, the second address generation circuit 52 mayinclude a fifth address output circuit 550, a sixth address outputcircuit 560, a seventh address output circuit 570 and an eighth addressoutput circuit 580.

The fifth address output circuit 550 may output the second write columnaddress signal WC<2> as the second bit C2_BG<1> of the first bank groupaddress signals C1_BG<1>, C2_BG<1>, C3_BG<1> and C4_BG<1>, if the firstwrite bank selection signal ALW<1> is enabled. The fifth address outputcircuit 550 may output the second read column address signal RC<2> asthe second bit C2_BG<1> of the first bank group address signalsC1_BG<1>, C2_BG<1>, C3_BG<1> and C4_BG<1>, if the first read bankselection signal ALR<1> is enabled.

The sixth address output circuit 560 may output the second write columnaddress signal WC<2> as the second bit C2_BG<2> of the second bank groupaddress signals C1_BG<2>, C2_BG<2>, C3_BG<2> and C4_BG<2>, if the secondwrite bank selection signal ALW<2> is enabled. The sixth address outputcircuit 560 may output the second read column address signal RC<2> asthe second bit C2_BG<2> of the second bank group address signalsC1_BG<2>, C2_BG<2>, C3_BG<2> and C4_BG<2>, if the second read bankselection signal ALR<2> is enabled.

The seventh address output circuit 570 may output the second writecolumn address signal WC<2> as the second bit C2_BG<3> of the third bankgroup address signals C1_BG<3>, C2_BG<3>, C3_BG<3> and C4_BG<3>, if thethird write bank selection signal ALW<3> is enabled. The seventh addressoutput circuit 570 may output the second read column address signalRC<2> as the second bit C2_BG<3> of the third bank group address signalsC1_BG<3>, C2_BG<3>, C3_BG<3> and C4_BG<3>, if the third read bankselection signal ALR<3> is enabled.

The eighth address output circuit 580 may output the second write columnaddress signal WC<2> as the second bit C2_BG<4> of the fourth bank groupaddress signals C1_BG<4>, C2_BG<4>, C3_BG<4> and C4_BG<4>, if the fourthwrite bank selection signal ALW<4> is enabled. The eighth address outputcircuit 580 may output the second read column address signal RC<2> asthe second bit C2_BG<4> of the fourth bank group address signalsC1_BG<4>, C2_BG<4>, C3_BG<4> and C4_BG<4>, if the fourth read bankselection signal ALR<4> is enabled.

Each of the third and fourth address generation circuits 53 and 54illustrated in FIG. 14 may be realized using substantially the samecircuit as the second address generation circuit 52 illustrated in FIG.17 except its input/output (I/O) signals. Thus, descriptions of thethird and fourth address generation circuits 53 and 54 will be omittedhereinafter.

Referring to FIG. 18, the fifth address output circuit 550 may include athird signal transmission circuit 5400, a fourth signal transmissioncircuit 5500 and a second buffer circuit 5600.

The third signal transmission circuit 5400 may receive the second writecolumn address signal WC<2> if the first write bank selection signalALW<1> has a logic “low” level. The third signal transmission circuit5400 may inversely buffer the second write column address signal WC<2>to generate a second transmission signal TS<2> if the first write bankselection signal ALW<1> has a logic “high” level. In an embodiment, thethird signal transmission circuit 5400 may also receive a complementaryfirst write bank selection signal ALWB<1>.

The fourth signal transmission circuit 5500 may receive the second readcolumn address signal RC<2> if the first read bank selection signalALR<1> has a logic “low” level. The fourth signal transmission circuit5500 may inversely buffer the second read column address signal RC<2> togenerate the second transmission signal TS<2> if the first read bankselection signal ALR<1> has a logic “high” level. In an embodiment, thefourth signal transmission circuit 5500 may also receive a complementaryfirst read bank selection signal ALRB<1>.

The second buffer circuit 5600 may inversely buffer the secondtransmission signal TS<2> to output the inversely buffered signal of thesecond transmission signal TS<2> as the second bit C2_BG<2> of the firstbank group address C1_BG<1>, C2_BG<1>, C3_BG<1> and C4_BG<1>.

Each of the sixth to eighth address output circuits 560, 570 and 580illustrated in FIG. 17 may be realized using substantially the samecircuit as the fifth address output circuit 550 illustrated in FIG. 18except its I/O signals. Thus, descriptions of the sixth to eighthaddress output circuits 560, 570 and 580 will be omitted hereinafter.

Operations of the semiconductor device having an aforementionedconfiguration will be described hereinafter with reference to FIG. 19 inconjunction with a column operation of a write operation for a firstbank group and a column operation of a read operation for a third bankgroup.

At a point of time “T1”, the first to N^(th) command/address signalsCA<1:N> may be inputted to the semiconductor device to perform the writeoperation. In such a case, the first to N^(th) command/address signalsCA<1:N> may have a logic level combination for performing the writeoperation with a burst length of ‘32’ (i.e., WT32). The burst length of‘32’ means that the number of bits included in data inputted to thesemiconductor device by one write command is thirty-two. In otherembodiments, the burst length may be more or less than ‘32.’

The command pulse generation circuit 1 may generate the first writecommand pulse EWT1 and the second write command pulse EWT2 according tothe first to N^(th) command/address signals CA<1:N>, the internal clocksignal ICLK and the inverted internal clock signal ICLKB.

At a point of time “T2”, the first and second command/address signalsCA<1:2> for selecting the first bank group BK1 as well as the thirdcommand/address signal CA<3> for selecting memory cells of the firstbank group BK1 among the third to sixth command/address signals CA<3:6>may be inputted to the command pulse generation circuit 1 insynchronization with a rising edge of the inverted internal clock signalICLKB.

At a point of time “T3”, the first to N^(th) command/address signalsCA<1:N> may be inputted to the command pulse generation circuit 1 toperform the write operation. In such a case, the first to NOcommand/address signals CA<1:N> may have a logic level combination forperforming the write operation with a burst length of ‘16’ (i.e., WT16).The burst length of ‘16’ means that the number of bits included in datainputted to the semiconductor device by one write command is sixteen.

The command pulse generation circuit 1 may generate the first writecommand pulse EWT1 and the second write command pulse EWT2 according tothe first to N^(th) command/address signals CA<1:N>, the internal clocksignal ICLK and the inverted internal clock signal ICLKB.

The flag signal generation circuit 2 may generate the write flag signalWTF at a point of time “T4” that a predetermined period elapses from thepoint of time “T1” that the first write command pulse EWT1 is generated.The write flag signal WTF may be generated from the first to N^(th)command/address signals CA<1:N> which are inputted at the point of time“T1” for the operation with the burst length of ‘32’.

The column control pulse generation circuit 3 may generate the writecolumn control pulse WTAYP at a point of time “T5” that a predeterminedperiod elapses from the point of time “T1” that the second write commandpulse EWT2 is generated. A period between the point of time “T1” and thepoint of time “T5” may be set as a write latency period.

The flag signal generation circuit 2 may generate the write flag signalWTF at a point of time “T6” that a predetermined period elapses from thepoint of time “T3” that the first write command pulse EWT1 is generated.The write flag signal WTF may be generated from the first to N^(th)command/address signals CA<1:N> which are inputted at the point of time“T3” for the operation with the burst length of ‘16’.

The write control circuit 10 may be synchronized with the write columncontrol pulse WTAYP to generate the first to fourth write column addresssignals WC<1:4> from the third to sixth command/address signals CA<3:6>inputted at the point of time “T2”. In such a case, the first writecolumn address signal WC<1> may be enabled to have a logic “low” level.

The write control circuit 10 may be synchronized with the write columncontrol pulse WTAYP generated at the point of time “T5” to generate thefirst to fourth write bank selection signals ALW<1:4> from the first andsecond command/address signals CA<1:2> inputted at the point of time“T2”. In such a case, the first write bank selection signal ALW<1> maybe enabled.

The first address output circuit 510 of the first address generationcircuit 51 may buffer the first write column address signal WC<1> tooutput the buffered signal of the first write column address signalWC<1> as the first bit C1_BG<1> of the first bank group address signalsC1_BG<1>, C2_BG<1>, C3_BG<1> and C4_BG<1> because the first write bankselection signal ALW<1> is enabled.

The first bank group BK1 of the core circuit 6 may perform the columnoperation based on the first bit C1_BG<1> having a logic “low” levelamong the bits included in the first bank group address signals. In sucha case, the first bank group BK1 of the core circuit 6 may operate withthe burst length of ‘16’ to store the data therein.

At a point of time “T7”, the first to N^(th) command/address signalsCA<1:N> may be inputted to the semiconductor device to perform the readoperation. In such a case, the first to N^(th) command/address signalsCA<1:N> may have a logic level combination for performing the readoperation with a burst length of ‘32’. The burst length of ‘32’ meansthat the number of bits included in data inputted to the semiconductordevice by one read command is thirty-two.

The command pulse generation circuit 1 may generate the first readcommand pulse ERD1 and the second read command pulse ERD2 according tothe first to N^(th) command/address signals CA<1:N>, the internal clocksignal ICLK and the inverted internal clock signal ICLKB.

At a point of time “T8”, the first and second command/address signalsCA<1:2> for selecting the third bank group BK3 as well as the thirdcommand/address signal CA<3> for selecting memory cells of the thirdbank group BK3 among the third to sixth command/address signals CA<3:6>may be inputted to the command pulse generation circuit 1 insynchronization with a rising edge of the inverted internal clock signalICLKB.

The flag signal generation circuit 2 may generate the read flag signalRDF at a point of time “T9” that a predetermined period elapses from thepoint of time “T7” that the first read command pulse ERD1 is generated.A period between the point of time “T7” and the point of time “T9” maybe set as a read latency period

The column control pulse generation circuit 3 may shift the write columncontrol pulse WTAYP, which is generated at the point of time “T5”, by apredetermined period to generate the internal write column control pulseIWTAYP at the point of time “T9”.

At a point of time “T10”, the write control circuit 10 may besynchronized with the internal write column control pulse IWTAYPgenerated at the point of time “T9” to generate the first to fourthinternal write bank selection signals IALW<1:4> from the first andsecond command/address signals CA<1:2>. In such a case, the firstinternal write bank selection signal IALW<1> may be enabled.

The first address output circuit 510 of the first address generationcircuit 51 may inversely buffer the first write column address signalWC<1> to output the inversely buffered signal of the first write columnaddress signal WC<1> as the first bit C1_BG<1> of the first bank groupaddress signals C1_BG<1>, C2_BG<1>, C3_BG<1> and C4_BG<1> because thefirst internal write bank selection signal IALW<1> is enabled.

The first bank group BK1 of the core circuit 6 may perform the columnoperation based on the first bit C1_BG<1> having a logic “high” levelamong the bits included in the first bank group address signals. In sucha case, the first bank group BK1 of the core circuit 6 may operate withthe burst length of ‘16’ to store the data therein. That is, the firstbank group BK1 of the core circuit 6 may operate with the burst lengthof ‘32’ through the operation performed with the burst length of ‘16’ atthe point of time “T6” and the operation performed with the burst lengthof ‘16’ at the point of time “T8”.

The column control pulse generation circuit 3 may generate the readcolumn control pulse RDAYP at a point of time “T11” that a predeterminedperiod elapses from the point of time “T7” that the second read commandpulse ERD2 is generated.

At a point of time “T12”, the read control circuit 20 may besynchronized with the read column control pulse RDAYP to generate thefirst to fourth read column address signals RC<1:4> from the third tosixth command/address signals CA<3:6> inputted at the point of time“T7”. In such a case, the first read column address signal RC<1> may beenabled to have a logic “high” level.

The read control circuit 20 may be synchronized with the read columncontrol pulse RDAYP generated at the point of time “T1” to generate thefirst to fourth read bank selection signals ALR<1:4> from the first andsecond command/address signals CA<1:2> inputted at the point of time“T8”. In such a case, the third read bank selection signal ALR<3> may beenabled.

The third address generation circuit 53 may buffer the first read columnaddress signal RC<1> to output the buffered signal of the first readcolumn address signal RC<1> as the first bit C1_BG<3> of the third bankgroup address signals C1_BG<3>, C2_BG<3>, C3_BG<3> and C4_BG<3> becausethe third read bank selection signal ALR<3> is enabled.

The third bank group BK3 of the core circuit 6 may perform the columnoperation based on the first bit C1_BG<3> having a logic “high” levelamong the bits included in the third bank group address signals. In sucha case, the third bank group BK3 of the core circuit 6 may operate withthe burst length of ‘16’ to output the data stored therein.

At a point of time “T13”, the flag signal generation circuit 2 may shiftthe read flag signal RDF, which is generated at the point of time “T9”,by a predetermined period to generate the internal read flag signalIRDF.

At a point of time “T14”, the column control pulse generation circuit 3may shift the read column control pulse RDAYP, which is generated at thepoint of time “T11”, by a predetermined period to generate the internalread column control pulse IRDAYP.

At a point of time “T15”, the read control circuit 20 may besynchronized with the internal read column control pulse IRDAYPgenerated at the point of time “T14” to generate the first to fourthinternal read bank selection signals IALR<1:4> from the first and secondcommand/address signals CA<1:2> inputted at the point of time “T8”. Insuch a case, the third internal read bank selection signal IALR<3> maybe enabled.

The first address output circuit 510 of the first address generationcircuit 51 may inversely buffer the first read column address signalRC<1> to output the inversely buffered signal of the first read columnaddress signal RC<1> as the first bit C1_BG<3> of the third bank groupaddress signals C1_BG<3>, C2_BG<3>, C3_BG<3> and C4_BG<3> because thethird internal read bank selection signal IALR<3> is enabled.

The third bank group BK3 of the core circuit 6 may perform the columnoperation based on the first bit C1_BG<3> having a logic “low” levelamong the bits included in the third bank group address signals. In sucha case, the third bank group BK3 of the core circuit 6 may operate withthe burst length of ‘16’ to output the data stored therein. That is, thethird bank group BK3 of the core circuit 6 may operate with the burstlength of ‘32’ through the operation performed with the burst length of‘16’ at the point of time “T12” and the operation performed with theburst length of ‘16’ at the point of time “T15”.

As described above, a semiconductor device according to an embodimentmay separate a path generating a signal for performing a columnoperation of a write operation and a path generating a signal forperforming a column operation of a read operation from each other andmay merge the signals for performing the column operations of the writeoperation and the read operation using an address generation circuit,thereby preventing the signals for performing the column operations ofthe write operation and the read operation from interfering with eachother.

The semiconductor devices described with reference to FIGS. 1 to 19 maybe applied to electronic systems that may include, for example, a memorysystem, a graphic system, a computing system, a mobile system, or thelike. For example, as illustrated in FIG. 20, an electronic system 1000according an embodiment may include a data storage circuit 1001, amemory controller 1002, a buffer memory 1003, and an input/output (I/O)interface 1004.

The data storage circuit 1001 may store data which are outputted fromthe memory controller 1002 or may read and output the stored data to thememory controller 1002, according to a control signal outputted from thememory controller 1002. The data storage circuit 1001 may include anonvolatile memory that can retain their stored data even when its powersupply is interrupted. The nonvolatile memory may be a flash memory suchas a NOR-type flash memory or a NAND-type flash memory, a phase changerandom access memory (PRAM), a resistive random access memory (RRAM), aspin transfer torque random access memory (STTRAM), a magnetic randomaccess memory (MRAM), or the like.

The memory controller 1002 may receive a command outputted from anexternal device (e.g., a host device) through the I/O interface 1004 andmay decode the command outputted from the host device to control anoperation for inputting data into the data storage circuit 1001 or thebuffer memory 1003 or for outputting the data stored in the data storagecircuit 1001 or the buffer memory 1003. Although FIG. 20 illustrates thememory controller 1002 with a single block, the memory controller 1002may include one controller for controlling the data storage circuit 1001and another controller for controlling the buffer memory 1003 comprisedof a volatile memory.

The buffer memory 1003 may temporarily store the data to be processed bythe memory controller 1002. That is, the buffer memory 1003 maytemporarily store the data which are outputted from or to be inputted tothe data storage circuit 1001. The buffer memory 1003 may store thedata, which are outputted from the memory controller 1002, according toa control signal. The buffer memory 1003 may read and output the storeddata to the memory controller 1002. The buffer memory 1003 may includethe semiconductor devices illustrated in FIG. 1. The buffer memory 1003may include a volatile memory such as a dynamic random access memory(DRAM), a mobile DRAM, or a static random access memory (SRAM).

The I/O interface 1004 may physically and electrically connect thememory controller 1002 to the external device (i.e., the host). Thus,the memory controller 1002 may receive control signals and data suppliedfrom the external device (i.e., the host) through the I/O interface 1004and may output the data outputted from the memory controller 1002 to theexternal device (i.e., the host) through the I/O interface 1004. Thatis, the electronic system 1000 may communicate with the host through theI/O interface 1004. The I/O interface 1004 may include any one ofvarious interface protocols such as a universal serial bus (USB), amulti-media card (MMC), a peripheral component interconnect-express(PCI-E), a serial attached SCSI (SAS), a serial AT attachment (SATA), aparallel AT attachment (PATA), a small computer system interface (SCSI),an enhanced small device interface (ESDI) and an integrated driveelectronics (IDE).

The electronic system 1000 may be used as an auxiliary storage device ofthe host or an external storage device. The electronic system 1000 mayinclude a solid state disk (SSD), a USB memory, a secure digital (SD)card, a mini secure digital (mSD) card, a micro secure digital (microSD) card, a secure digital high capacity (SDHC) card, a memory stickcard, a smart media (SM) card, a multi-media card (MMC), an embeddedmulti-media card (eMMC), a compact flash (CF) card, or the like.

What is claimed is:
 1. A semiconductor device comprising: a controlcircuit configured to generate a write column address signal from acommand and address (command/address) signal and to generate a writebank selection signal and an internal write bank selection signal fromthe command/address signal during a write operation and configured togenerate a read column address signal from the command/address signaland to generate a read bank selection signal and an internal read bankselection signal from the command/address signal during a readoperation, wherein the write bank selection signal and the internalwrite bank selection signal are sequentially enabled, and wherein theread bank selection signal and the internal read bank selection signalare sequentially enabled; and an address generation circuit configuredto output the write column address signal as a bank group address signalin synchronization with the write bank selection signal and the internalwrite bank selection signal or configured to output the read columnaddress signal as the bank group address signal in synchronization withthe read bank selection signal and the internal read bank selectionsignal.
 2. The semiconductor device of claim 1, wherein the readoperation is preceded by the write operation.
 3. The semiconductordevice of claim 1, wherein the control circuit includes: a write controlcircuit configured to be synchronized with a write column control pulseand an internal write column control pulse to generate the write columnaddress signal, the write bank selection signal and the internal writebank selection signal from the command/address signal; and a readcontrol circuit configured to be synchronized with a read column controlpulse and an internal read column control pulse to generate the readcolumn address signal, the read bank selection signal and the internalread bank selection signal from the command/address signal.
 4. Thesemiconductor device of claim 3, wherein the write column control pulseand the internal write column control pulse are sequentially enabledduring the write operation; and wherein the read column control pulseand the internal read column control pulse are sequentially enabledduring the read operation.
 5. The semiconductor device of claim 3,wherein the command/address signal includes a first command/addresssignal and a second command/address signal; and wherein the writecontrol circuit includes: a write bank control circuit configured tolatch the first command/address signal in synchronization with a writeflag signal and an internal write flag signal when a write command pulseis enabled to perform the write operation and configured to generate thewrite bank selection signal and the internal write bank selection signalfrom the latched signal of the first command/address signal insynchronization with the write column control pulse and the internalwrite column control pulse; and a write column control circuitconfigured to generate the write column address signal from the secondcommand/address signal in synchronization with the write column controlpulse and the internal write column control pulse when the write commandpulse is inputted to the write column control circuit.
 6. Thesemiconductor device of claim 5, wherein the write bank control circuitincludes: a first pipe control circuit configured to generate a firstinput control signal and a first output control signal which are enabledin synchronization with the write flag signal and the internal writeflag signal when the write command pulse is inputted to the first pipecontrol circuit; a first pipe circuit configured to latch the firstcommand/address signal in synchronization with the first input controlsignal and configured to output the latched signal of the firstcommand/address signal as a write bank address signal in synchronizationwith the first output control signal; a write delay circuit configuredto delay the write column control pulse and the internal write columncontrol pulse to generate a write latch pulse and an internal writelatch pulse; and a write bank selection signal generation circuitconfigured to generate the write bank selection signal, insynchronization with the write latch pulse, from the write bank addresssignal, and configured to generate the internal write bank selectionsignal, in synchronization with the internal write latch pulse, from thewrite bank address signal.
 7. The semiconductor device of claim 5,wherein the write column control circuit includes: a second pipe controlcircuit configured to generate a second input control signal and asecond output control signal which are enabled in synchronization withthe write column control pulse and the internal write column controlpulse when the write command pulse is inputted to the second pipecontrol circuit; and a second pipe circuit configured to latch thesecond command/address signal in synchronization with the second inputcontrol signal and configured to output the latched signal of the secondcommand/address signal as the write column address signal insynchronization with the second output control signal.
 8. Thesemiconductor device of claim 3, wherein the command/address signalincludes a first command/address signal and a second command/addresssignal; and wherein the read control circuit includes: a read bankcontrol circuit configured to latch the first command/address signal insynchronization with a read flag signal and an internal read flag signalwhen a read command pulse is enabled to perform the read operation andconfigured to generate the read bank selection signal and the internalread bank selection signal from the latched signal of the firstcommand/address signal in synchronization with the read column controlpulse and the internal read column control pulse; and a latch circuitconfigured to generate the read column address signal from the secondcommand/address signal in synchronization with the read column controlpulse when the read command pulse is inputted to the latch circuit. 9.The semiconductor device of claim 8, wherein the read bank controlcircuit includes: a third pipe control circuit configured to generate athird input control signal and a third output control signal which areenabled in synchronization with the read flag signal and the internalread flag signal when the read command pulse is inputted to the thirdpipe control circuit; a third pipe circuit configured to latch the firstcommand/address signal in synchronization with the third input controlsignal and configured to output the latched signal of the firstcommand/address signal as a read bank address signal in synchronizationwith the third output control signal; a read delay circuit configured todelay the read column control pulse and the internal read column controlpulse to generate a read latch pulse and an internal read latch pulse;and a read bank selection signal generation circuit configured togenerate the read bank selection signal, in synchronization with theread latch pulse, from the read bank address signal and configured togenerate the internal read bank selection signal, in synchronizationwith the internal read latch pulse, from the read bank address signal.10. A semiconductor device comprising: a control circuit configured togenerate first and second write column address signals, first and secondwrite bank selection signals and first and second internal write bankselection signals from a command and address (command/address) signalduring a write operation and configured to generate first and secondread column address signals, first and second read bank selectionsignals and first and second internal read bank selection signals fromthe command/address signal during a read operation; an addressgeneration circuit configured to output the first and second writecolumn address signals as first and second bank group address signals insynchronization with the first and second write bank selection signalsand the first and second internal write bank selection signals orconfigured to output the first and second read column address signals asthe first and second bank group address signals in synchronization withthe first and second read bank selection signals and the first andsecond internal read bank selection signals; and a core circuitconfigured to include a first bank group and a second bank group,wherein the first bank group performs the write operation and the readoperation when the first bank group address signal is enabled, andwherein the second bank group performs the write operation and the readoperation when the second bank group address signal is enabled.
 11. Thesemiconductor device of claim 10, wherein the first bank group and thesecond bank group sequentially store data during the write operation;and wherein the first bank group and the second bank group sequentiallyoutput the data stored therein during the read operation.
 12. Thesemiconductor device of claim 10, wherein the control circuit includes:a write control circuit configured to be synchronized with a writecolumn control pulse and an internal write column control pulse togenerate the first and second write column address signals, the firstand second write bank selection signals and the first and secondinternal write bank selection signals from the command/address signal;and a read control circuit configured to be synchronized with a readcolumn control pulse and an internal read column control pulse togenerate the first and second read column address signals, the first andsecond read bank selection signals and the first and second internalread bank selection signals from the command/address signal.
 13. Thesemiconductor device of claim 12, wherein the write column control pulseand the internal write column control pulse are sequentially enabledduring the write operation; and wherein the read column control pulseand the internal read column control pulse are sequentially enabledduring the read operation.
 14. The semiconductor device of claim 12,wherein the command/address signal includes a first command/addresssignal and a second command/address signal; and wherein the writecontrol circuit includes: a write bank control circuit configured tolatch the first command/address signal in synchronization with a writeflag signal and an internal write flag signal when a write command pulseis enabled to perform the write operation and configured to generate thefirst and second write bank selection signals and the first and secondinternal write bank selection signals from the latched signal of thefirst command/address signal in synchronization with the write columncontrol pulse and the internal write column control pulse; and a writecolumn control circuit configured to generate the first and second writecolumn address signals from the second command/address signal insynchronization with the write column control pulse and the internalwrite column control pulse when the write command pulse is inputted tothe write column control circuit.
 15. The semiconductor device of claim14, wherein the write bank control circuit includes: a first pipecontrol circuit configured to generate a first input control signalwhich is enabled in synchronization with the write flag signal and afirst output control signal which is enabled in synchronization with theinternal write flag signal when the write command pulse is inputted tothe first pipe control circuit; a first pipe circuit configured to latchthe first command/address signal in synchronization with the first inputcontrol signal and configured to output the latched signal of the firstcommand/address signal as first and second write bank address signals insynchronization with the first output control signal; a write delaycircuit configured to delay the write column control pulse and theinternal write column control pulse to generate a write latch pulse andan internal write latch pulse; and a write bank selection signalgeneration circuit configured to generate the first and second writebank selection signals, in synchronization with the write latch pulse,from the first and second write bank address signals and configured togenerate the first and second internal write bank selection signals, insynchronization with the internal write latch pulse, from the first andsecond write bank address signals.
 16. The semiconductor device of claim15, wherein the write bank selection signal generation circuit includes:a first write bank selection signal generation circuit configured togenerate the first write bank selection signal which is enabled insynchronization with the write latch pulse and to generate the firstinternal write bank selection signal which is enabled in synchronizationwith the internal write latch pulse, when the first and second writebank address signals have a first logic level combination; and a secondwrite bank selection signal generation circuit configured to generatethe second write bank selection signal which is enabled insynchronization with the write latch pulse and to generate the secondinternal write bank selection signal which is enabled in synchronizationwith the internal write latch pulse, when the first and second writebank address signals have a second logic level combination.
 17. Thesemiconductor device of claim 14, wherein the write column controlcircuit includes: a second pipe control circuit configured to generate asecond input control signal and a second output control signal which areenabled in synchronization with the write column control pulse and theinternal write column control pulse when the write command pulse isinputted to the second pipe control circuit; and a second pipe circuitconfigured to latch the second command/address signal in synchronizationwith the second input control signal and configured to output thelatched signal of the second command/address signal as the first andsecond write column address signals in synchronization with the secondoutput control signal.
 18. The semiconductor device of claim 12, whereinthe command/address signal includes a first command/address signal and asecond command/address signal; and wherein the read control circuitincludes: a read bank control circuit configured to latch the firstcommand/address signal in synchronization with a read flag signal and aninternal read flag signal when a read command pulse is enabled toperform the read operation and configured to generate the first andsecond read bank selection signals and the first and second internalread bank selection signals from the latched signal of the firstcommand/address signal in synchronization with the read column controlpulse and the internal read column control pulse; and a latch circuitconfigured to generate the first and second read column address signalsfrom the second command/address signal in synchronization with the readcolumn control pulse when the read command pulse is inputted to thelatch circuit.
 19. The semiconductor device of claim 18, wherein theread bank control circuit includes: a third pipe control circuitconfigured to generate a third input control signal and a third outputcontrol signal which are enabled in synchronization with the read flagsignal and the internal read flag signal when the read command pulse isinputted to the third pipe control circuit; a third pipe circuitconfigured to latch the first command/address signal in synchronizationwith the third input control signal and configured to output the latchedsignal of the first command/address signal as first and second read bankaddress signals in synchronization with the third output control signal;a read delay circuit configured to delay the read column control pulseand the internal read column control pulse to generate a read latchpulse and an internal read latch pulse; and a read bank selection signalgeneration circuit configured to generate the first and second read bankselection signals, in synchronization with the read latch pulse, fromthe first and second read bank address signals and configured togenerate the first and second internal read bank selection signals, insynchronization with the internal read latch pulse, from the first andsecond read bank address signals.
 20. The semiconductor device of claim19, wherein the read bank selection signal generation circuit includes:a first read bank selection signal generation circuit configured togenerate the first read bank selection signal which is enabled insynchronization with the read latch pulse and to generate the firstinternal read bank selection signal which is enabled in synchronizationwith the internal read latch pulse, when the first and second read bankaddress signals have a first logic level combination; and a second readbank selection signal generation circuit configured to generate thesecond read bank selection signal which is enabled in synchronizationwith the read latch pulse and to generate the second internal read bankselection signal which is enabled in synchronization with the internalread latch pulse, when the first and second read bank address signalshave a second logic level combination.
 21. The semiconductor device ofclaim 10, wherein the address generation circuit includes: a firstaddress generation circuit configured to be synchronized with the firstand second write bank selection signals and the first and secondinternal write bank selection signals to output the first write columnaddress signal as a first bit of the first and second bank group addresssignals or configured to be synchronized with the first and second readbank selection signals and the first and second internal read bankselection signals to output the first red column address signal as thefirst bit of the first and second bank group address signals; and asecond address generation circuit configured to be synchronized with thefirst and second write bank selection signals to output the second writecolumn address signal as a second bit of the first to fourth bank groupaddress signals or configured to be synchronized with the first andsecond read bank selection signals to output the second read columnaddress signal as the second bit of the first and second bank groupaddress signals.
 22. The semiconductor device of claim 21, wherein thefirst address generation circuit includes: a first address outputcircuit configured to buffer the first write column address signal tooutput the buffered signal of the first write column address signal as afirst bit of the first bank group address signal when the first writebank selection signal is enabled, configured to inversely buffer thefirst write column address signal to output the inversely bufferedsignal of the first write column address signal as the first bit of thefirst bank group address signal when the first internal write bankselection signal is enabled, configured to buffer the first read columnaddress signal to output the buffered signal of the first read columnaddress signal as the first bit of the first bank group address signalwhen the first read bank selection signal is enabled, and configured toinversely buffer the first read column address signal to output theinversely buffered signal of the first read column address signal as thefirst bit of the first bank group address signal when the first internalread bank selection signal is enabled; and a second address outputcircuit configured to buffer the first write column address signal tooutput the buffered signal of the first write column address signal as afirst bit of the second bank group address signal when the second writebank selection signal is enabled, configured to inversely buffer thefirst write column address signal to output the inversely bufferedsignal of the first write column address signal as the first bit of thesecond bank group address signal when the second internal write bankselection signal is enabled, configured to buffer the first read columnaddress signal to output the buffered signal of the first read columnaddress signal as the first bit of the second bank group address signalwhen the second read bank selection signal is enabled, and configured toinversely buffer the first read column address signal to output theinversely buffered signal of the first read column address signal as thefirst bit of the second bank group address signal when the secondinternal read bank selection signal is enabled.
 23. The semiconductordevice of claim 21, wherein the second address generation circuitincludes: a third address output circuit configured to buffer the secondwrite column address signal to output the buffered signal of the secondwrite column address signal as a second bit of the first bank groupaddress signal when the first write bank selection signal is enabled andconfigured to buffer the second read column address signal to output thebuffered signal of the second read column address signal as the secondbit of the first bank group address signal when the first read bankselection signal is enabled; and a fourth address output circuitconfigured to buffer the second write column address signal to outputthe buffered signal of the second write column address signal as asecond bit of the second bank group address signal when the second writebank selection signal is enabled and configured to buffer the secondread column address signal to output the buffered signal of the secondread column address signal as the second bit of the second bank groupaddress signal when the second read bank selection signal is enabled.